Published on Sep 16, 2019
The high growth of the semiconductor industry over the past two decades has put Very Large Scale Integration in demand all over the world. Digital Signal Processing has played a great role in expanding VLSI device area.
The recent rapid advancements in multimedia computing and high speed wired and wireless communications made DSP to grab increased attention.
For an N-point transformation the direct computation of the Discrete Fourier Transform (DFT) requires N 2 operations. Cooley and Turkey explained the concept of Fast Fourier Transform (FFT) which reduces the order of computation to Nlog 2 N. The FFT is not an approximation of the DFT, it's exactly equal to the DFT. FFT decomposes the set of data to be transformed into a series of smaller data sets to be transformed.
The size of FFT decomposition is called "radix". Then, it decomposes those smaller sets into even smaller sets. At each stage of processing, the results of the previous stage are combined with twiddle factor multiplication.
Finally, FFT is calculated for each small data set. Generally, FFT's can be decomposed using DFT's of even and odd points, which is called a Decimation-In-Time (DIT) FFT, or they can be decomposed using a first-half/second-half approach, which is called a "Decimation-In-Frequency" (DIF) FFT.
A large number of FFT algorithms have been developed, but among all radix-4 are most widely used for practical applications due to their simple architecture, with constant butterfly geometry and the possibility of performing them 'in place'. The algorithm for 16-point radix-4 FFT can be implemented with decimation either in time or frequency. In this work, the decimation in time (DIT) technique will be adopted in order to implement the 16-point radix-4 FFT
• Fourier transform play an important role in many digital signal processing applications which includes acoustic, optics, telecommunications, speech, signal and image processing.
The efficient computation handled in FFT, reduces the burden in the real world application
VHDL
Simulation: modelsim5.8c
Synthesis: Xilinx 9.1
